An SRAM elementary memory cell is a volatile memory cell, i.e., losing its data in the event of a loss of power, but offering a very high access speed and an infinite cycling. A non-volatile elementary memory cell, for example an EEPROM memory cell, allows the datum to be saved in the event of a loss of power, but cannot be cycled indefinitely.
A memory cell associating an SRAM elementary cell and one or more non-volatile cells (for example two or four) allows the performances of the two approaches to be cumulated, i.e., the speed and the infinite endurance of the SRAM memory and the non-volatility of the non-volatile memory, for example the flash or EEPROM memory.
Under normal operating conditions, the writing and reading of a datum in a memory cell of this type are carried out in the SRAM elementary cell. Conversely, notably in the event of a loss of power, the contents of the SRAM elementary cell are transferred into the non-volatile elementary memory cell(s) associated with it.
Then, notably when power is restored, the data contained in the non-volatile memory cells are reloaded into the corresponding SRAM elementary memory cell.
Examples of architectures of memory cells of this type associating an SRAM memory and a non-volatile memory are described in U.S. Pat. Nos. 4,132,904; 4,467,451; 4,980,859; 7,164,608; and 8,018,768 and in the French patent applications filed under the numbers FR1355439 and FR1355440.
Some embodiments of these structures described in these documents present a data inversion in the reloading of the SRAM memory by the contents of the associated non-volatile memory.